system level design造句
例句與造句
- The partition of software / hardware and the architecture design of hardware are completed in the system level design of line
在頂層設(shè)計(jì)完成了軟硬件劃分和硬件體系架構(gòu)，根據(jù)硬件架構(gòu)進(jìn)行功能模塊的劃分并選用適當(dāng)?shù)膇p 。 - Systemc is a system level design language which can be used efficiently in hardware / software co - design and co - simulation . it extends the abilities to describe hardware systems in the basis of c + + language
Systemc是一種適合于進(jìn)行硬軟件協(xié)同設(shè)計(jì)和模擬的語言，它在c + +語言的基礎(chǔ)上擴(kuò)充了硬件系統(tǒng)的描述功能。 - 5 the conception that top - down system level design and bottom - up building library are parallel operations is proposed for the first time , and the conception of parallel design flow is brought forward according to this
85 、提出了自上而下的系統(tǒng)設(shè)計(jì)與自下而上的建庫是并行操作的概念，并據(jù)此提出并行設(shè)計(jì)流程的概念。 。 - 3 the conception and methodology on orthogonalization of separation between ip mapping and platform mapping in system level design is proposed for the first time . and a new platform based on design flow is brought forward according to this conception
3 、提出了系統(tǒng)級(jí)設(shè)計(jì)中ip映射與平臺(tái)映射分離的正交設(shè)計(jì)概念和方法， 11合肥工業(yè)大學(xué)博士學(xué)位論文并據(jù)此提出了新的基于平臺(tái)的設(shè)計(jì)流程。 - System level design . in this level , the thesis provides the system partition method , function design and method of design based on finite state machine . the key is the modification of available soft ip and realization of ad bus reuse technology
系統(tǒng)級(jí)設(shè)計(jì)：論述了pci安全芯片的系統(tǒng)劃分、功能設(shè)計(jì)和基于有限狀態(tài)機(jī)的設(shè)計(jì)思想，重點(diǎn)是對(duì)已有ip的修改方法和ad總線再復(fù)用技術(shù)的實(shí)現(xiàn)。 - It's difficult to find system level design in a sentence. 用system level design造句挺難的
- The main work of this thesis includes : system level design and implementta - tion of an underwater multiple targets tracking ( umtt ) system , use of the embedded dgps receiver in buoy , migration of wireless communication system on ocean , and performance verification by experiments
本論文的主要工作包括水下多目標(biāo)跟蹤系統(tǒng)的總體設(shè)計(jì)研究與實(shí)現(xiàn)，浮標(biāo)中嵌入式dgps接收機(jī)的使用和海上無線通信系統(tǒng)的搭建，最后通過實(shí)驗(yàn)驗(yàn)證系統(tǒng)的工作性能。 - The test results indicate the sensor networks object tracking system is sensitive to the cost of sensors and synchronization of time windows , furthermore , it validates that embed system level design methodology based on ptolemy can direct wireless sensor networks system design correctly and feasibly
測(cè)試結(jié)果表明:無線傳感器網(wǎng)絡(luò)目標(biāo)定位系統(tǒng)對(duì)于無線傳感器節(jié)點(diǎn)的功耗及信息時(shí)間同步窗口具有敏感性,符合無線傳感器網(wǎng)絡(luò)目標(biāo)定位系統(tǒng)應(yīng)用特性,驗(yàn)證ptolemy嵌入式系統(tǒng)級(jí)設(shè)計(jì)方法學(xué)對(duì)于指導(dǎo)無線傳感器網(wǎng)絡(luò)系統(tǒng)設(shè)計(jì)的正確性和可行性。 - The paper discusses the design and implementation of wireless sensor networks system based on system level design methodology , doing research about the embedded system level design methodology based on ptolemy ii , and using hierarchical heterogeneity design methodology based on ptolemy ii to guide the design of wireless sensor networks system
本文主要研究無線傳感器網(wǎng)絡(luò)系統(tǒng)在嵌入式系統(tǒng)建模仿真平臺(tái)ptolemyii下系統(tǒng)級(jí)建模設(shè)計(jì)與實(shí)現(xiàn)。研究ptolemyii嵌入式系統(tǒng)級(jí)設(shè)計(jì)方法學(xué),并遵循ptolemyii所采用的層次異構(gòu)的設(shè)計(jì)思想,指導(dǎo)并完成無線傳感器網(wǎng)絡(luò)系統(tǒng)模型的設(shè)計(jì)與實(shí)現(xiàn)。 - The quadrilateral mesh and a special kind of linear basis function is selected on the rooftop so that the treatment of the attachment of the wire antenna to the surface patch is easier than other methods reported in literatures . using the proposed method , the analyses and prediction of electro - magnetic compatibility of the electrically small conducting structure are achieved , which provides a theoretical guidance in the system level design
在使用矩量法的過程中，山于在金屬物體表面運(yùn)用四邊形面元進(jìn)行剖分，并在面元上選擇了一種特殊的線性基函數(shù)，園時(shí)在細(xì)天線和面元的連接處使用了改進(jìn)了的方法，使得在處理細(xì)天線與面元電流相連接的部分較之以往文獻(xiàn)提到的方法更為簡單。 - Currently , a new design methodology - system level design methodology is introduced into the wireless sensor network system modeling and simulation methodology , system level design methodologies look upon wireless sensor networks system as a complete system , with an embedded systems perspective to divide wireless sensor networks system into some modules which have independent system behavior and uniformly modeling , covering the traditional shortcomings of single modeling for wireless sensor networks system . therefore , it is significant to study the sensor networks system system - level design methodology , which will lay solid basis of heterogeneous environment system theory research
近來,一種新的設(shè)計(jì)方法學(xué)-系統(tǒng)級(jí)設(shè)計(jì)方法學(xué)被引入無線傳感器網(wǎng)絡(luò)的建模仿真方法學(xué)中,系統(tǒng)級(jí)設(shè)計(jì)方法學(xué)將無線傳感器網(wǎng)絡(luò)看作一個(gè)完整的系統(tǒng),以嵌入式系統(tǒng)的觀點(diǎn)將無線傳感器網(wǎng)絡(luò)系統(tǒng)分成各個(gè)系統(tǒng)行為獨(dú)立的模塊進(jìn)行統(tǒng)一建模,彌補(bǔ)了傳統(tǒng)無線傳感器網(wǎng)絡(luò)系統(tǒng)單一建模的缺點(diǎn),因此研究無線傳感器網(wǎng)絡(luò)系統(tǒng)級(jí)設(shè)計(jì)方法學(xué),在異構(gòu)環(huán)境下對(duì)無線傳感器網(wǎng)絡(luò)系統(tǒng)進(jìn)行建模仿真具有重要的理論和實(shí)際意義。 - It is a complete pci interface circuit which including pci master , pci slave and pci arbiter . a design method of circuit multiplexing and that pci slave holds priority are proposed in system level design . a design method of pci slave which based on multi state machine structure and pci arbiter which based on hybrid algorithm of static - dynamic arbitration are proposed in the algorithmic level design
這是一個(gè)包括從pci 、主pci和pci仲裁器的完整的pci接口電路，系統(tǒng)級(jí)設(shè)計(jì)中提出了電路復(fù)用和從pci優(yōu)先的設(shè)計(jì)思路；算法級(jí)設(shè)計(jì)中提出了基于多狀態(tài)機(jī)結(jié)構(gòu)的從pci設(shè)計(jì)方法、基于靜-動(dòng)態(tài)混合仲裁算法的pci仲裁器設(shè)計(jì)方法。 - This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no . 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education , prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation . the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design
本文基于以下科研項(xiàng)目撰寫：國家自然科學(xué)基金“深亞微米超高速多媒體芯片設(shè)計(jì)理論的研究” ( 69876010 )國家863計(jì)劃“超大規(guī)模集成電路ip核接口及相關(guān)設(shè)計(jì)技術(shù)” ( 863 - soc - y - 3 - 1 )國家“九五”重點(diǎn)科技攻關(guān)“ mcu高層語言描述及其嵌入技術(shù)研究” ( 97 - 758 - 01 - 53 - 08 )國家教育部“ soc軟硬件集成協(xié)同設(shè)計(jì)和驗(yàn)證優(yōu)化理論和方法研究” (教技司[ 2001 ] 215 )國家科技學(xué)術(shù)著作出版基金“ verilog與pc機(jī)接口電路設(shè)計(jì)” ( 99 - f - 1 - 011 )論文的主要工作和取得的成果如下： 1 、在研究集成電路設(shè)計(jì)方法學(xué)發(fā)展歷史的基礎(chǔ)上，提出了設(shè)計(jì)的積木化原則和積木元件最大化原則。 - Contrapose to the instability of the third - order charge - pump pll system , the loop optimization method is employed in system level design to decide the bandwidth and phase margin , therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system . according to tsmc 0 . 35 m sige bicmos model , the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre
5 .根據(jù)tsmc0 . 35 msigebicmos工藝模型,利用cadencespectre模擬軟件對(duì)所設(shè)計(jì)的電荷泵鎖相環(huán)路中各個(gè)模塊及整個(gè)系統(tǒng)進(jìn)行了模擬仿真,模擬結(jié)果顯示,在1 . 5v電源電壓下,頻率為200mhz的參考輸入信號(hào),輸出中心頻率為800mhz ,分頻電路采用4分頻,環(huán)路帶寬為10mhz ,捕獲時(shí)間大約為0 . 92 s ,功耗大約為15mw ,達(dá)到了設(shè)計(jì)指標(biāo)。